1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to integrated circuit fabrication processes and structures.
2. Description of the Background Art
Integrated circuits fabricated using complementary metal oxide semiconductor (CMOS) technology have traditionally employed a single N+ doped polysilicon gate material for both N-channel metal oxide semiconductor (NMOS) and P-channel metal oxide semiconductor (PMOS) transistors. Due to the work function of N+ polysilicon, this results in a surface-channel NMOS transistor and a buried-channel PMOS transistor. The surface-channel NMOS transistor typically has good short-channel characteristics and can be scaled to gate dimensions of 0.1 μm and below. The buried-channel PMOS transistor typically has poor short-channel characteristics and, as a result, is designed with a larger threshold voltage than the surface-channel NMOS transistor to limit sub-threshold leakage current. Thus, the threshold voltage of a PMOS transistor is typically about 0.2 V larger than the threshold voltage of an NMOS transistor of the same gate length in order to produce the same off-state leakage current. For integrated circuits using supply voltages of 3.3 V or higher, the larger threshold voltage of the buried-channel PMOS is generally not a problem and good performance can be achieved. However, as the supply voltage scales below 3.3 V, the higher threshold voltage starts to have a significant effect on performance.
To improve PMOS transistor performance, a so-called “dual gate” approach may be used to fabricate CMOS integrated circuits requiring supply voltages of 2.5 V and below. The dual gate approach involves the use of N+ doped polysilicon gate for the NMOS transistor and P+ doped polysilicon gate for the PMOS transistor. The use of P+ polysilicon produces a surface-channel PMOS transistor that improves short-channel characteristics and enables the threshold voltage of the PMOS transistor to be reduced to about the same value as the NMOS transistor. Unfortunately, the dual gate approach is not feasible in some applications. For example, the dual gate approach is not typically implemented in CMOS memory applications due to constraints imposed by the memory cell architecture and requirements. As a result, many memory applications have continued to use a single N+ doped polysilicon gate material for both NMOS and PMOS transistors even as power supply voltages have scaled down to 1.8 V.
From the foregoing, a technique for improving the performance of buried-channel transistors is highly desirable.